Electrostatic Discharge (ESD) is a rapid discharge that flows between two objects due to the built-up of static charge. ESD may destroy semiconductor devices because the rapid discharge can produce a relatively large current. In order to reduce the semiconductor failures due to ESD, ESD protection circuits have been developed to provide a current discharge path. When an ESD event occurs, the discharge current is conducted through the discharge path without going through the internal circuits to be protected.
In the semiconductor technology, NMOS transistors, Silicon-Controlled Rectifiers (SCRs) and RC triggered PMOS transistors are widely used. However, with the advance of submicron semiconductor processes, the existing ESD protection solutions may not meet the ever-increasing requirements from the semiconductor industry. For example, in a high voltage application, SCR or NMOS based ESD protection circuits may cause a latch-up failure because the holding voltage is not high enough. On the other hand, despite having a relatively high holding voltage, a RC triggered PMOS transistor may consume a large die area. Furthermore, a variety of applications require different ESD protection holding voltages. The existing ESD solutions may not provide various ESD protection holding voltages based upon a basic ESD protection structure.
Corresponding numerals and symbols in the different figures generally refer to corresponding parts unless otherwise indicated. The figures are drawn to clearly illustrate the relevant aspects of the various embodiments and are not necessarily drawn to scale.